Emerging applications in various electronic and biomedical fields require miniaturized capacitors with relatively high densities and high volumetric efficiencies. Implantable biomedical applications, for example, currently demand ultra-high capacitance densities with relatively low leakage currents at relatively high voltages. Conventional approaches to achieve high capacitance densities have sought to enhance one or more of three fundamental parameters: (a) higher permittivity dielectrics, (b) thinner films, and (c) enhancement in surface area. The first parameter is material-chemistry dependent and the second and third parameters are process-dependent. Advancements in conventional high-density capacitors have mainly been achieved in three types of devices: (1) trench capacitors, (2) multilayer ceramic capacitors, and (3) tantalum capacitors. FIG. 1 provides a graph of these three conventional capacitor architectures and the relationship between the area enhancement factor and the planar capacitance densities enabled by these devices. As shown in FIG. 1, certain conventional tantalum capacitors have been able to achieve effective capacitance densities of up to 40 μF/cm2, with an area enhancement factor of up to around 100. Similarly, as shown in FIG. 1, certain conventional silicon trench capacitors have been able to achieve capacitance densities of between 2-40 μF/cm2, with an area enhancement factor of up to around 50 for a device thickness of about 100 microns. Furthermore, certain conventional multilayer ceramic capacitors silicon trench capacitors have been able to achieve capacitance densities of around 40 μF/cm2, with an area enhancement factor of up to around 40. While each of these areas of high-density capacitor development exhibit certain benefits advantages over prior designs, they are still largely insufficient to meet the demands of emerging applications.
The first category of conventional capacitors, trench capacitors, attempt to leverage the fundamental parameter of enhancement in surface area to increase capacitance density. As shown in FIG. 2, a silicon trench capacitor can be created by micromachining silicon and creating a three-dimensional surface. These silicon trenches are often etched by either a wet etching or a dry etching process. Once the trench has been etched, a thermal oxidation, nitradation, or oxynitradation process can be implemented to provide the dielectric layer for the insulator. By relying on developments in low-cost deep etching techniques and moderate k dielectric films, conventional trench capacitors have reached densities of as much as 40 μF/cm2 with a stack of three trench capacitors.
While suitable for certain implementations, trench capacitors fail to meet the requirements for many applications because they cannot provide the capacitance density required and the volumetric efficiency required. Trench capacitors fail to meet the volumetric efficiency required for many applications because there is an elastic relationship between the depth of the trench and the capacitance density of the trench capacitor. Therefore, higher capacitance requires a deeper trench and an increase in the volume of the device.
The second category of capacitors, multilayer ceramic capacitors or MLCCs, attempt to provide high-density capacitive structures by implementing a stack of metal and dielectrics, comprised of ceramic material. As shown in FIG. 3, these layers can be stacked alternatively to form a multilayered capacitor. Conventional multilayer ceramic capacitors have reduced the thickness of the dielectric layers to permit an increase in the number of layers in the same die size package; thus, increasing the capacitance density of the package. The ability to fabricate thin dielectric layers of ceramic materials is heavily dependent upon the ability to create highly dispersed, fine-grained ceramic powders. Furthermore, the volumetric efficiency of the multilayer ceramic capacitors increases with a reduction in electrode and dielectric thickness. Conventional multilayer ceramic capacitors fabrication processes have successfully achieved dielectric and electrode thickness of around 2 to 3 microns, resulting in 30 to 50 layers for a 100 micron capacitor device, which can provide a capacitance density of around 60 μF/cm2.
While suitable for certain implementations, multilayer ceramic capacitors fail to meet the requirements for many applications because they cannot provide the capacitance density required, the volumetric efficiency required, and they are not often silicon compatible. The fabrication of multilayer ceramic capacitors is a highly complex process due to the multiple layers of the device. Furthermore, MLCC fabrication must be carried out at high temperatures, which are incompatible with silicon-based implementations. Additionally, multilayer ceramic capacitors require oxidation resistant electrodes to preserve the integrity of the device. Furthermore, one of the most significant drawbacks to multilayer ceramic capacitors architectures is that they require lead connections, which limit the volumetric efficiency of the device and can result in reliability issues.
The third category of conventional capacitors, tantalum capacitors, attempt to optimize the surface area of the tantalum powder used as the electrode for the capacitor to achieve high capacitive densities. As shown in FIG. 4, the bottom electrode of a conventional tantalum capacitor can be comprised of a pellets of grains or flakes of tantalum powder. These pellets, shown in FIG. 4, of tantalum powder typically contain voids which can be leveraged by a conformal dielectric to increase the surface area of the capacitive component. Certain conventional tantalum capacitor implementations have achieved a capacitance density of around 20 μF/cm2 for Break Down Voltage (“BDV”) value of 15. In 6 V implementations, conventional tantalum capacitors have achieved an equivalent capacitance density of around 140 μF/cm2.
While suitable for certain implementations, tantalum capacitors fail to meet the requirements for many applications because they cannot provide the capacitance density required, the volumetric efficiency required, and they are not silicon compatible. The fabrication of tantalum capacitors requires sintering of the tantalum pellets at temperatures of around 1900° C., which is incompatible with silicon-based implementations. Additionally, the dielectric is formed through an anodization, creating tantalum oxide, which has disadvantages as a dielectric material because the device has poor reliability under certain polarity conditions. Furthermore, one of the most significant drawbacks to tanatalum capacitor architectures is that it cannot be sintered on a silicon carrier which makes it difficult to pattern and form independent electrodes. Another major fundamental limitation is that conventional tanatalum capacitor architectures are limited to tantalum oxide dielectrics.
Therefore, it would be advantageous to provide an apparatus and method for efficiently and effectively providing high-density capacitors.
Additionally, it would be advantageous to provide an apparatus and method to provide a thin, planar high-density capacitor interposer that can be implemented in a silicon compatible processes.
Additionally, it would be advantageous to provide an improved system and method for providing a high-density capacitor with independent terminals and discrete capacitor components.